As a background of the invention, a configuration of a DRAM including equalizers on far-end and near-end sides of bit lines, respectively, as seen from a sense amplifier, will be described with reference to FIG. 1 which is referred to in a description about the present invention as well. FIG. 1 is a diagram showing a general configuration of the sense amplifier that amplifies memory cell data in the DRAM.
Referring to FIG. 1, signals DT and DB are the signals on one and the other of a bit line pair. Reference characters SAP and SAN denote control signals for activating and deactivating a sense amplifier 20. Reference characters PDLF and PDLN denote control signals for performing on/off control of equalizers (equalizing elements) N3 and N4, respectively, which equalize the bit lines DT and DB. Reference characters WL1 and WL2 denote word lines. A memory cell in a memory array 10 includes a capacitor (memory capacitor) that stores data and a memory cell transistor that has a gate connected to a corresponding word line, has one of a drain and a source connected to a corresponding bit line, and has the other of the drain and the source connected to the capacitor. The equalizing elements N3 and N4 are connected between bit line pair DT and DB. Gates of the equalizing elements N3 and N4 are connected to the control signals PDLF and PDLN, respectively. When the equalizing elements N3 and N4 are turned on, the equalizing elements N3 and N4 equalize electric potentials of the bit line pair DT and DB. The sense amplifier 20 includes PMOS transistors P1 and P2 which have sources connected in common to the control signal SAP and NMOS transistors N1 and N2 which have drains connected to drains of the PMOS transistors P1 and P2, respectively. Gates of the PMOS transistor P1 and the NMOS transistor N1 are connected in common to a common connecting node between the drains of the PMOS transistors P1 and P2. Gates of the PMOS transistor P2 and the NMOS transistor N2 are connected in common to a common connecting node between the drains of the PMOS transistor P1 and the NMOS transistor N1. A common connecting node between the drains of the PMOS transistor P2 and the NMOS transistor N2 is connected to the bit line DT, while a common connecting node between the drains of the PMOS transistor P1 and the NMOS transistor N1 is connected to the bit line DB. The PMOS transistor P1 and the NMOS transistor N1 constitute a first CMOS inverter, while the PMOS transistor P2 and the NMOS transistor N2 constitute a second CMOS inverter. An output of the first CMOS inverter is connected to an input of the second CMOS inverter and an input of the second CMOS inverter is connected to an input of the first CMOS inverter, thereby forming a latch circuit (flip-flop).
Next, an operation of FIG. 1 will be described with reference to a timing chart in FIG. 4. In FIG. 4, (A) shows a waveform of a clock and command, (B) shows waveforms of the control signals PDLN and PDLF, (C) shows waveforms of word lines 1 and 2, (D) shows waveforms of the bit lines DT and DB at a time of a normal operation, and (E) shows waveforms of the bit lines DT and DB when a defect is present in one of the equalizing elements. A description will be given below about a case where an active command (ACT) and a precharge command (PRE) are been input in the order of ACT, PRE, and ACT. Though a READ/WRITE command is input between the ACT command and the next PRE command, illustration of the READ/WRITE command is not performed in FIG. 4 for simplicity of the description. The same holds true in FIGS. 5 through 9.
Before the first ACT is input, the DRAM is in a precharged state. In the precharged state, all word lines are kept LOW, the control signals PDLF and PDLN are kept HIGH, the NMOS transistors N3 and N4 are kept on, and the bit lines DT and DB are in an equalized state. During a precharge period, the power supply to the control signals SAP and SAN is stopped (and the control signals SAP and SAN are at an intermediate level between High and Low levels). The sense amplifier 20 is deactivated, and an output of the sense amplifier is in an off state (floating state) and has the same potential as the bit lines.
In the following description, it is assumed that an external address associated with the word line I is input when the first-time ACT command has been input (that is, when the ACT command has been input, a ROW address is input from an address signal terminal not shown). When the ACT command is received, the control signals PDLF and PDLN are switched from HIGH to LOW in order to cancel the equalization of the bit lines.
Then, the selected word line (WL1) is activated and set to a HIGH level. Then, memory cell transistors with gates thereof connected to the selected word line 1 (WL1) are turned on. Due to electric charge in the memory cell capacitor, a minute difference potential is generated between the bit line DT and the bit line DB to which a memory cell transistor in an on state is connected. Then, the control signal SAP is set to HIGH, and the control signal SAN is set to LOW to activate the sense amplifier 20. Amplification of the minute difference potential between the bit lines DT and DB by the sense amplifier 20 is started.
Then, when the amplification of the voltage between the bit lines DT and DB by the sense amplifier 20 is continued, the potentials of the bit lines DB and DT get to SAP and SAN levels, respectively.
Next, when the PRE command is received, the selected word line 1 (WL1) is first brought into a deactivated state (LOW level) from an activated state (HIGH level), and the memory cell transistor is turned off. After the word line (WL1) has been driven LOW, the control signals SAP and SAN are electrically disconnected from the power supply. The sense amplifier 20 is thereby deactivated. The control signals PDLF and PDLN are switched from LOW to HIGH. The equalizing element N3 and N4 are turned on, thereby starting equalization of the pair of the bit lines DT and DB.
An equalizing time of the pair of the bit lines DT and DB determines basic performance of the DRAM such as tRP (time from issuing of the precharge command to issuing of the subsequent active command). For this reason, when a bit line length is long, an approach is sometimes employed in which the equalizing elements N3and N4 are installed on the far-end and near-end sides of the bit lines, respectively, as shown in FIG. 1, thereby reducing the time tRP.